- Introduced June 8, 1978
- Clock rates:
- 5 MHz with 0.33 MIPS
- 8 MHz with 0.66 MIPS
- 10 MHz with 0.75 MIPS
- The memory is divided into odd and even banks. It accesses both the banks simultaneuosly in order to read 16 bit of data in one clock cycle.
- Bus Width 16 bits data, 20 bits address
- Number of Transistors 29,000 at 3 µm
- Addressable memory 1 megabyte
- Up to 10X the performance of 8080 (typically lower)
- Used in portable computing, and in the IBM PS/2 Model 25 and Model 30. Also used in the AT&T PC6300 / Olivetti M24, a popular IBM PC-compatible (predating the IBM PS/2 line.)
- Used segment registers to access more than 64 KB of data at once, which many programmers complained made their work excessively difficult.
[edit] 8088
- Introduced June 1, 1979
- Clock rates:
- 4.77 MHz with 0.33 MIPS
- 9 MHz with 0.75 MIPS
- Internal architecture 16 bits
- External bus Width 8 bits data, 20 bits address
- Number of Transistors 29,000 at 3 µm
- Addressable memory 1 megabyte
- Identical to 8086 except for its 8 bit external bus (hence an 8 instead of a 6 at the end)
- Used in IBM PCs and PC clones
[edit] MCS-86 Family
- 8086-CPU
- 8087-Math-CoProcessor
- 8088-CPU
- 8089-Input/Output Co-Processor
- 8208-Dynamic RAM Controller
- 8284-Clock Generator & Driver
- 8286-Octal Bus Transceiver
- 8287-Octal Bus Transceiver
- 8288-Bus Controller
- 8289-Bus Arbiter
[edit] 80186
- Introduced 1982
- Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor (These were at fixed addresses which differed from the IBM PC, making it impossible to build a 100% PC-compatible computer around the 80186.)
- Added a few opcodes and exceptions to the 8086 design; otherwise identical instruction set to 8086 and 8088.
- Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like
- Used in several non-PC-Compatible MS-DOS computers including RM Nimbus, Tandy 2000
- Later renamed the iAPX 186
[edit] 80188
- A version of the 80186 with an 8-bit external data bus
- Later renamed the iAPX 188
[edit] 80286
- Introduced February 1, 1982
- Clock rates:
- 6 MHz with 0.9 MIPS
- 8 MHz, 10 MHz with 1.5 MIPS
- 12.5 MHz with 2.66 MIPS
- 16 MHz, 20 MHz and 25 MHz available.
- Bus Width 16 bits
- Included memory protection hardware to support multitasking operating systems with per-process address space
- Number of Transistors 134,000 at 1.5 µm
- Addressable memory 16 MB (16 MB)
- Added protected-mode features to 8086 with essentially the same instruction set
- 3-6X the performance of the 8086
- Widely used in IBM-PC AT and AT clones contemporary to it
0 comments:
Post a Comment