Pentium II and III Xeon

• PII Xeon
  • Variants
    • 400 MHz Introduced June 29, 1998
    • 450 MHz (512 KB L2 Cache) Introduced October 6, 1998
    • 450 MHz (1 MB and 2 MB L2 Cache) Introduced January 5, 1999
• PIII Xeon
  • Introduced October 25, 1999
  • Number of transistors: 9.5 million at 0.25 µm or 28 million at 0.18 µm)
  • L2 cache is 256 KB, 1 MB, or 2 MB Advanced Transfer Cache (Integrated)
  • Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
  • System Bus clock rate 133 MHz (256 KB L2 cache) or 100 MHz (1 - 2 MB L2 cache)
  • System Bus Width 64 bit
  • Addressable memory 64 GB
  • Used in two-way servers and workstations (256 KB L2) or 4- and 8-way servers (1 - 2 MB L2)
  • Family 6 model 10
  • Variants
    • 500 MHz (0.25 µm process) Introduced March 17, 1999
    • 550 MHz (0.25 µm process) Introduced August 23, 1999
    • 600 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
    • 667 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
    • 733 MHz (0.18 µm process, 256 KB L2 cache) Introduced October 25, 1999
    • 800 MHz (0.18 µm process, 256 KB L2 cache) Introduced January 12, 2000
    • 866 MHz (0.18 µm process, 256 KB L2 cache) Introduced April 10, 2000
    • 933 MHz (0.18 µm process, 256 KB L2 cache)
    • 1000 MHz (0.18 µm process, 256 KB L2 cache) Introduced August 22, 2000
    • 700 MHz (0.18 µm process, 1 - 2 MB L2 cache) Introduced May 22, 2000