Celeron (Pentium II-based)

• Covington - 0.25 µm process technology
  • Introduced April 15, 1998
  • 242-pin Slot 1 SEPP (Single Edge Processor Package)
  • Number of transistors 7.5 million
  • 66 MHz system bus clock rate
  • Slot 1
  • 32 KB L1 cache
  • No L2 cache
  • Variants
    • 266 MHz Introduced April 15, 1998
    • 300 MHz Introduced June 9, 1998
• Mendocino - 0.25 µm process technology
  • Introduced August 24, 1998
  • 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
  • Number of transistors 19 million
  • 66 MHz system bus clock rate
  • Slot 1, Socket 370
  • 32 KB L1 cache
  • 128 KB integrated cache
  • Family 6 model 6
  • Variants
    • 300 A MHz Introduced August 24, 1998
    • 333 MHz Introduced August 24, 1998
    • 366 MHz Introduced January 4, 1999
    • 400 MHz Introduced January 4, 1999
    • 433 MHz Introduced March 22, 1999
    • 466 MHz
    • 500 MHz Introduced August 2, 1999
    • 533 MHz Introduced January 4, 2000
    • 266 MHz (Mobile)
    • 300 MHz (Mobile)
    • 333 MHz (Mobile) Introduced April 5, 1999
    • 366 MHz (Mobile)
    • 400 MHz (Mobile)
    • 433 MHz (Mobile)
    • 450 MHz (Mobile) Introduced February 14, 2000
    • 466 MHz (Mobile)
    • 500 MHz (Mobile) Introduced February 14, 2000